IBM Introduces New Chip Design Verification Software

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HAIFA, ISRAEL - 09 Jun 2004: IBM today announced it has developed chip design verification software that is expected to shorten the design cycle and help produce higher quality chips.

IBM's new technology takes the technique of "formal verification," which involves exhaustive analysis of very large chips designs prior to fabrication, to new levels.

Among the benefits of a recent patent awarded to IBM in this area is the ability of the designer to rapidly test specific execution patterns of interest, aiding in the detection of evasive design flaws that would be very difficult to find using traditional simulation methods.

As the chip design industry faces manufacturing hurdles to get new features and performance gains onto chips, IBM is leaping over the silicon scaling challenges by pushing the leading edge of chip design capabilities. Pioneering new technologies, such as those in the area of formal verification, IBM is turning to new electronic design automation (EDA) design tools and methodologies embodying these technologies to handle higher degrees of complexity, while reducing costs and cycle times.

"This technology harnesses the power of formal verification and makes it a mainstream design tool," said Yaron Wolfsthal, senior manager of Formal Verification and Testing Technologies in the IBM Haifa Research Lab. "The availability of this capability during the design phase can help designers gain immediate insight into the behavior of their design, changing it dynamically to meet the requirements."

New Technology Overcomes Limitations
With the level of complexity of chip designs increasing, the costs and time delays associated with correcting a design flaw once the design has been committed to actual production in silicon can be prohibitive. While formal verification techniques existed previously, the technologies to support this type of up-front analysis were too slow and complex to use fully as a routine part of the design process. The new IBM technology overcomes those limitations, allowing for more extensive checks of chip designs before manufacture.

The new design technology was developed by researchers at the IBM Haifa Research Lab where a staff of some 100 engineers and chip design verification professionals work on developing and supporting verification solutions for IBM's business units. Earlier this year, IBM announced the general availability of RuleBase Parallel Edition platform for IBM partners and customers, which supports the Accellera standard PSL language, while harnessing the power of parallel computing. Using PSL, which is based on the Sugar language from IBM, designers can now more easily specify the scenarios they wish to examine as they follow the design methodology facilitated by the new IBM formal verification technology.

"We continue to innovate in the areas of chip design using formal verification technology and building on our field expertise gained in the verification of IBM microprocessors," said Dr. Michael Rodeh, Director of the IBM Haifa Research Lab. "This innovative design approach will help us beat the silicon slowdown and demonstrates our continued commitment to serving our customers by rapidly bringing state-of-the-art design technologies to the marketplace."

The newly-announced verification technology, previously available only to IBM engineers, is expected to be employed by IBM's customers and partners worldwide. IBM has announced a program under which its customers can upgrade from the previous generation of IBM's formal verification product to RuleBase Parallel Edition.


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