IBM Announces World's Smallest Working Silicon Transistor

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Yorktown Heights, N.Y - 09 Dec 2002: IBM today announced the world's smallest working silicon transistor. With this transistor IBM has been able to push silicon to limits on a molecular scale not previously achieved.

At six nanometers in length, this new transistor is at least 10 times smaller than the state-of-the-art transistors in production today. A nanometer (nm) is one billionth of a meter. The Consortium of International Semiconductor Companies in its 2001 International Technology Roadmap for Semiconductors projected that transistors have to be smaller than 9 nanometers by 2016 in order to continue the performance trend. IBM is the first company to make working transistors below that gate length.

"The ability to build working transistors at these dimensions could allow us to put 100 times more transistors into a computer chip than is currently possible," said Dr. Randy Isaac, vice president of science and technology, IBM Research. "Moreover, this achievement underscores the fundamental challenges of scaling, namely power density, that must be addressed as silicon is pushed to molecular dimensions."

Transistor scaling, or the reduction of the gate length (the size of the switch that turns transistors on and off), improves the performance and speed of chips as well as lowers their manufacturing cost and power consumption per switching event. The IT industry has been scaling down transistors for the past 30 years to meet demand for smaller and more intelligent electronic devices.

Scaling to this new molecular level demonstrates that the basic transistor concept still functions at this size. Continued innovation will be required to simultaneously achieve high performance and to manage power density and heat dissipation. The IBM results will lead to further research into small, high-density silicon devices and allow scientists to introduce new structures and new materials.

Technical details: Creating the smallest transistors
For decades the industry has recognized the limitations of scaling, especially because smaller transistors are more difficult to turn on and off. In this work, IBM has been able to address this concern by reducing the silicon thickness on the silicon-on-isulator (SOI) wafers. The silicon body of IBM's new 6nm gate transistor is only 4-8nm thick and has proper turn-on and turn-off behavior. IBM's new 6nm gate transistor has a silicon layer only 4-8nm thick yet retains proper turn-on and turn-off behavior.

IBM researchers made these world-record, ultra-thin silicon channel devices and circuits on bonded silicon-on-insulator (SOI) wafers using halo implants and 248nm-wavelength lithography. With more aggressive halo, the IBM team has produced the smallest working MOSFETs reported to date , with 4nm silicon body and 6nm gate lengths. IBM's result suggests that aggressive thinning of the SOI layer is a promising option to drive CMOS device scaling.

IBM will present details of this research breakthrough in a paper entitled "Extreme Scaling with Ultra-thin Silicon Channel MOSFETs" at the International Electron Devices Meeting (IEDM) being held from December 9-11 in San Francisco. This project was a collaboration between IBM Research and IBM Microelectronics, and is one of many to be presented at IEDM. Downloadable images related to the paper are available at: