IBM Creates New Dimension for High-Performance Chips

Research Breakthrough Opens New Door in Chip Performance Race

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Yorktown Heights, NY, USA - 11 Nov 2002: IBM today announced that it has developed a new technique for building three-dimensional (3D) integrated circuits (ICs) that will help increase chip performance, functionality and density. This technique is an essential step toward successful realization of high performance 3D ICs.

Today’s microchips are two-dimensional: the transistors are in one plane and a multi-layer system of wires is used to connect different parts of the chip. Opening up a third dimension for integrated circuits creates new opportunities to increase chip performance, functionality and device packing density by

“Traditionally, decreasing transistor size and wire lengths produces faster, more powerful chips,” said Dr. John Warlaumont, Director of Silicon Technology at IBM Research. “However, it is becoming more difficult to reap performance gains from these traditional ‘scaling’ techniques because the transistor dimensions are reaching fundamental physical limitations. IBM’s development of this new technique for building 3D integrated circuits opens new avenues for chip performance improvements.”

Despite the compelling potential advantages of the 3D IC, it has not yet been adopted as a mainstream technology primarily because of the fabrication challenges this new circuit design imposes. For instance, many research groups take the “bottom-up” approach to building 3D ICs, in which each device layer is fabricated sequentially, starting with the bottom-most layer. Unfortunately, the quality of each new layer of silicon that is grown or deposited on top of the existing devices is typically worse than the original silicon layer. Also, many of the processes required for building devices on each subsequent layer can degrade the devices below, making this approach unsuitable for high performance technology.

IBM’s new technique for building 3D ICs based on the layer transfer of completed circuits involves transferring functional circuits (many transistors and several wiring levels) from one wafer to another and connecting the multiple layers electrically to form the 3D chip. The key to this transfer is a wafer-level bonding approach that joins high performance device layers fabricated by conventional means.

For the first time in semiconductor history, IBM demonstrates that the processes required for stacking active device layers can preserve the electrical integrity of short-channel silicon metal oxide semiconductor field effect transistors (MOSFETs) and ring oscillator circuits. The layer transfer technique uses only low process temperatures and mechanical stresses to preserve the sensitive devices on the silicon wafers. IBM has shown that state-of-the-art 130 nm silicon-on-insulator (SOI) devices with IBM’s proprietary copper metallization and “low-k” dielectric insulators can withstand the transfer processes.

IBM will present details of the technique in a paper, titled "Electrical Integrity of State-of-the-Art 0.13 µm SOI CMOS Devices and Circuits Transferred for Three-Dimensional (3D) Integrated Circuit (IC) Fabrication" at the International Electron Devices Meeting (IEDM) held in San Francisco, Dec. 9-11, 2002. This project was supported in part by DARPA and was a collaboration between IBM Research and IBM Microelectronics.

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