IBM Technology Cuts Time, Cost of System-on-a-Chip Designs

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FISHKILL, N.Y - 21 Jun 1999: . . . IBM today announced technology designed to reduce advanced "system-on-a-chip" development time and cost by as much as 50 percent.

Faster, cheaper availability of specialized chips can help electronics manufacturers transform standalone products into pervasive computing devices, boost the speed of Internet communications gear and provide new options for e-business applications.

"IBM is at the forefront of a revolution in the custom chip industry," said John Kelly, general manager, IBM Microelectronics. "We're changing the way systems and chips are designed to satisfy the insatiable demand for high-performance electronics. With our wealth of technologies and system design experience, IBM is uniquely positioned to lead this transformation."

Highlights of the announcement include:

-- an IBM chip technology that allows pieces of chip designs (or "cores") from multiple sources to be plugged together more easily to create entire new chips;

-- IBM's architecture for building highly-integrated chips quickly and efficiently using this technology;

-- the first example of such a chip from IBM: a new, high-performance PowerPC embedded microprocessor that incorporates a host of additional features.

Key to the announcement is CoreConnect, an IBM-developed "on-chip bus" standard. An on-chip bus is a communications link that provides a way for pieces of chip design to be connected together to form a whole new chip. However, in the past, the variety of bus technologies in use by chip-makers often made their designs incompatible.

Where industry efforts to standardize had failed, IBM has established a de facto bus standard by openly publishing specifications, licensing the technology at no cost and gaining the endorsement of major chip designers. In a separate announcement, a number of major chip designers and intellectual property providers disclosed plans to support the CoreConnect bus and to work with IBM to drive its further evolution.

Using CoreConnect to plug together pieces of chip design, IBM also announced plans to build a series of pre-configured, pre-tested base model chips called "superstructures." Superstructures are chips designed for particular applications with many of the features most often required already built in. Where additional functions are needed, superstructures can be easily customized rather than having to create a whole new chip from scratch, speeding delivery and reducing cost.

All superstructures will be pre-tested to verify that their component parts work together. Pre-verification can significantly reduce chip design time, given that up to 50 percent of a typical custom chip's design cycle can be spent on testing.

With this announcement, IBM also introduced the first of these superstructures, called the PowerPC 405GP. The 405GP is a standard product that combines a high-performance PowerPC microprocessor (up to 266 MHz) with a number of complementary features, all on a single chip. While the added features provide many of the functions typically required in a variety of applications, such as in networking products, the chip can be readily modified to add unique features for specific customers.

"Using its superstructure design approach, IBM was able to take the PowerPC 405GP through design and deliver parts to us in a timely basis to meet our product needs," said Terrel Jones, director of hardware development at 3Com. "The 405GP contains the extra functions and features we would normally be able to get only through a ground-up custom design, yet at a cost and turnaround time more like that of an off-the-shelf product. What's more, if our needs change as our product designs evolve, IBM can use the 405GP superstructure as a means to rapidly respond."

IBM is a leading provider of custom chips for servers, storage systems, wired and wireless communications, and pervasive computing products. For more information about these and other products and services from IBM Microelectronics, visit

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