IBM Announces Open On-Chip Bus Architecture

Leading IP Providers Adopt Standard for Chip Design

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FISHKILL, N.Y - 21 Jun 1999: . . . IBM today simplified the custom chip design process by introducing an open on-chip bus architecture called CoreConnect that is compliant with Virtual Socket Interface Alliance (VSIA) guidelines and immediately available at no licensing or royalty cost to chip designers and core IP and tool developers. IBM also announced formation of the CoreConnect users group, a consortium of leading IP and service providers, led by Mentor Graphics Corporation and Cadence Design Systems, Inc., who have adopted the CoreConnect bus and plan to work with IBM to drive its continued evolution.

CoreConnect provides a method for assembling pieces of chip designs from diverse suppliers and facilitates an open system-on-a-chip design process that encourages development of reusable IP. While previous industry standards efforts failed to gain broad acceptance, IBM has established CoreConnect as a de facto bus standard by openly publishing specifications, licensing the technology at no cost and gaining the endorsement of major chip designers. In addition to Cadence and Mentor, Lexra Inc., Stellar Semiconductor, Summit Design and Technical Data Freeway have licensed the CoreConnect bus and will be participating in the users group.

IBM's CoreConnect bus has served as a foundation for more than 20 chip designs over the last two years using cores from the IBM Blue Logic™ core library. The availability of CoreConnect as a standard bus now provides designers access to an even broader, industry-wide library of proven cores that are ready for rapid assimilation into chip designs, thereby improving the speed at which system-on-a-chip projects can be completed.

"Building a common bridge between independent IP providers is an attractive solution for third-party vendors, as well as system architects," stated Mick O'Brien, general manager for the Intellectual Property and Physical Libraries Divisions of Mentor Graphics. "Since the complexity of chip design is evolving to a point where designers are assembling IP from a variety of sources, there is a need for standardization in the development process. Adopting IBM's CoreConnect bus into the Inventra portfolio makes our offering more attractive to customers by enabling them to focus on product differentiation rather than verification and function issues."

IP providers are accelerating industry-wide acceptance of the CoreConnect bus due to its potential reduction in the amount of work required to enable the reuse of IP in multiple designs.

"Cadence sees the CoreConnect technology as a valuable option in the design of complex SOC devices," said Bob Wiederhold, corporate vice president of Worldwide Design Services at Cadence. "The combination of IBM's technology and Cadence design skills can enable us to quickly and efficiently meet our customers' needs for SOC design."

The availability of CoreConnect as a processor independent, open bus architecture has also attracted the attention of processor IP vendors.

"Standard architectures are key to success in our business, and Lexra sees tremendous value in the openness of CoreConnect," said Charlie Cheng, president and CEO of Lexra, Inc. "By supporting this open architecture, we give our customers the ability to integrate our processor IP and other independent cores without encountering the obstacles and constraints of meeting multiple protocols."

In a related announcement today, IBM introduced the PowerPC™ 405GP, a high performance, highly integrated PowerPC embedded processor that was designed using the CoreConnect bus. The 405GP features a significant number of integrated peripheral functions typically required by a variety of applications, so it can be readily modified for specific customer applications. This rapid modification is possible, in part, through the use of CoreConnect as an open bus architecture.

The IBM CoreConnect bus includes the processor local bus (PLB), on chip peripheral bus (OPB), a bus bridge, two arbiters, and a device control register (DCR) bus. High performance peripherals connect to the high bandwidth, low latency PLB. Slower peripheral cores connect to the OPB, which reduces traffic on the PLB, resulting in greater overall system performance. IBM is licensing the arbiter and bridge macros, bus monitors, and bus functional language compiler of 32- and 64-bit versions of CoreConnect at no charge. The CoreConnect specification is available on the Internet at

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