IBM Takes Next Step in Opening Power Architecture to Research and Education Community

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PALO ALTO, CA - 14 Dec 2005: At a event in Palo Alto, California today, IBM announced plans to make the specifications of IBM's PowerPC 405 core freely available to researchers and academia.

IBM plans to coordinate the contribution of the 405 core through, which was formed one year ago to enable and promote Power Architecture technology as the preferred collaborative hardware development platform for the electronics industry.

The move is in response to requests by leading educators in computer science and participants in collaborative multi-core processing research projects, such as the Research Accelerator for Multiple Processors (RAMP). RAMP is led by the University of California Berkeley, Stanford University, Massachusetts Institute of Technology (MIT), Carnegie Mellon University (CMU), University of Texas -Austin and the University of Washington.

RAMP researchers will now be able to map this core into their FPGA-based systems (Field Programmable Gate Arrays), for new chip architecture experiments.

"Access to this Power Architecture technology and the large, diverse Power Architecture community will help enable our vision," said Professor David A. Patterson, University of California Berkeley. "RAMP is a broad collaboration to deliver an extremely flexible, low-cost platform for experimenting with massively parallel systems on a chip."

"The contribution of the IBM PowerPC 405 core will allow researchers and educators to better explore new computing architectures for massively parallel systems and accelerators, and assist software developers in experimenting with new programming models on these systems," said Nigel Beck, chairman, "This family of cores is at the heart of networking and communications devices ranging from gaming consoles to the BlueGene/L supercomputer."

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