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Preparing test wafers with 5nm silicon nanosheet transistors

  • Preparing test wafers with 5nm silicon nanosheet transistors

    Preparing test wafers with 5nm silicon nanosheet transistors

    Date added: 05 Jun 2017

    IBM scientists at the SUNY Polytechnic Institute Colleges of Nanoscale Science and Engineering’s NanoTech Complex in Albany, NY prepare test wafers with 5nm silicon nanosheet transistors, loaded into the front opening unified pod, or FOUPs, to test an industry-first process of building 5nm transistors using silicon nanosheets. (Credit: Connie Zhou)