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Wafer of chips with 5nm silicon nanosheet transistors

  • Wafer of chips with 5nm silicon nanosheet transistors

    Wafer of chips with 5nm silicon nanosheet transistors

    Date added: 05 Jun 2017

    IBM Research scientist Nicolas Loubet holds a wafer of chips with 5nm silicon nanosheet transistors manufactured using an industry-first process that can deliver 40 percent performance enhancement at fixed power, or 75 percent power savings at matched performance. (Credit: Connie Zhou)