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The embedded marketplace has a long history of SoC designs, which are enabled with a central processor, a standard bus and I/O cores that interface to that standard bus.
CoreConnect
IBM's standard PowerPC® bus, has been freely licensed to over 1500 IP developers in the past decade, creating one of the world's largest I/O core ecosystems. In addition, with each Power Design Kit, IBM provides a bridge to ARM's ecosystem of I/O core partners, enabling their use in Power-based designs.
IBM and our ecosystem of I/O partners shown below, also provide native CoreConnect I/Os for all latency-sensitive IP so that your SoC designs can be optimized.
For more information about cores which generally impact system performance see the range of available native
CoreConnect™ cores.
AMBA
For information about cores which do not generally impact system performance, see the full line of AMBA compliant cores available through
Synopsys.
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