CoreConnect bus architecture

The award-winning IBM CoreConnect™ bus architecture eases the integration and reuse of processor, system, and peripheral cores within standard product and custom system-on-a-chip (SOC) designs. The versatility of CoreConnect bus architecture allows engineers to assemble custom SOC designs using cores designed to CoreConnect specifications. With time-consuming performance, functional, and timing pattern issues resolved, designers can focus on product differentiation — dramatically reducing costs and time-to-market for simple and complex SOC designs.

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The CoreConnect bus architecture is a standard SOC design point, and serves as the foundation of IBM Blue Logic® or other non-IBM devices. Elements of this architecture include the processor local bus (PLB), the on-chip peripheral bus (OPB), a bus bridge, and a device control register (DCR) bus. High-performance peripherals connect to the high-bandwidth, low-latency PLB. Slower peripheral cores connect to the OPB, which reduces traffic on the PLB, resulting in greater overall system performance.

Bus model toolkits are available to assist in designing custom logic to the PLB/OPB/DCR bus standards.

Features

• Fully synchronous, supports up to 8 masters
• 32-, 64-, and 128-bit architecture versions; extendable to 256-bit
• Separate read/write data buses, enables overlapped transfers and higher data rates
• High bandwidth capabilities
  • Burst transfers, variable and fixed-length supported
  • Pipelining
  • Split transactions
  • DMA transfers
  • No on-chip tri-states required
  • Cache Line transfers
  • Overlapped arbitration, programmable priorty fairness

• Provides fully synchronous movement of GPR data between CPU and slave logic

• Identifies possible problems at an early stage in the design cycle
• Protocol monitors enable verification of new cores
• Design example of how to use buses
• System performance analysis

Performance features
Feature	CoreConnect 32	CoreConnect 64	CoreConnect 128
PLB width	32-Bit	64-Bit	128-Bit
Max frequency	66 MHz	133 MHz	183 MHz *
Max bandwidth	264 MB/s	800 MB/s	2.9 GB/s *
* estimated

Third parties providing CoreConnect cores:

• Denali
• Jennic
• SafeNet

Additional CoreConnect licensing information.