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z/VM V4 R2.0 LSPR ITR Ratios for IBM Processors

  

All capacity numbers are relative to the IBM 2064-1C1. The data represents z/VM V4 R2.0 (z/Architecture) workload running on the 9672 G5 and G6 processors in 31-bit real addressing mode. The 2064 and 2066 processors are running in 64-bit real addressing mode. Information presented in this table is current as of December 3, 2002.

Note: Please contact your IBM marketing representative to insure that you are using the most current data. Proper use of this data requires an understanding of the LSPR methodology.

     Table of Contents

IBM S/390 Multiprise 3000
IBM S/390 G5 Enterprise Server
IBM S/390 G5 Turbo Enterprise Server
IBM S/390 G6 Enterprise Server
IBM S/390 G6 Turbo Enterprise Server
zSeries 800
zSeries 900 Models 1XX
zSeries 900 Models 2XX

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IBM S/390 Multiprise 3000 (zSeries 900 2064-1C1 = 1.00)
Processor #CP MSU CMS1
7060-H30 1 NA 0.25
7060-H50 1 NA 0.49
7060-H70 2 NA 0.89

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IBM S/390 G5 Enterprise Server (zSeries 900 2064-1C1 = 1.00)
Processor #CP MSU CMS1
9672-RA6 1 15 0.36
9672-R16 1 20 0.48
9672-RB6 2 28 0.71
9672-R26 2 37 0.95
9672-RC6 3 55 1.40
9672-RD6 4 71 1.81
9672-T16 1 22 0.52
9672-T26 2 41 1.02
9672-R36 3 59 1.51
9672-R46 4 76 1.99
9672-R56 5 93 2.45
9672-R66 6 109 2.91
9672-R76 7 124 3.36
9672-R86 8 136 3.76
9672-R96 9 146 3.99
9672-RX6 10 156 4.14

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IBM S/390 G5 Turbo Enterprise Server (zSeries 900 2064-1C1 = 1.00)
Processor #CP MSU CMS1
9672-Y16 1 26 0.62
9672-Y26 2 48 1.21
9672-Y36 3 70 1.80
9672-Y46 4 90 2.37
9672-Y56 5 109 2.92
9672-Y66 6 128 3.47
9672-Y76 7 146 4.00
9672-Y86 8 161 4.47
9672-Y96 9 174 4.75
9672-YX6 10 186 4.92

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IBM S/390 G6 Enterprise Server (zSeries 900 2064-1C1 = 1.00)
Processor #CP MSU CMS1
9672-X17 1 30 0.71
9672-X27 2 57 1.38
9672-X37 3 80 2.04
9672-X47 4 103 2.69
9672-X57 5 126 3.32
9672-X67 6 148 3.94
9672-X77 7 169 4.51
9672-X87 8 188 5.03  a
9672-X97 9 205 5.46  a
9672-XX7 10 221 5.83  a
9672-XY7 11 235 6.13  a
9672-XZ7 12 248 6.37  a

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IBM S/390 G6 Turbo Enterprise Server (zSeries 900 2064-1C1 = 1.00)
Processor #CP MSU CMS1
9672-Z17 1 35 0.81
9672-Z27 2 67 1.59
9672-Z37 3 95 2.34
9672-Z47 4 123 3.08
9672-Z57 5 149 3.81
9672-Z67 6 174 4.51
9672-Z77 7 197 5.17
9672-Z87 8 217 5.76  a
9672-Z97 9 236 6.25  a
9672-ZX7 10 254 6.69  a
9672-ZY7 11 270 7.02  a
9672-ZZ7 12 285 7.30  a

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zSeries 800 (zSeries 900 2064-1C1 = 1.00)
Processor #CP MSU CMS1
2066-0E1 1 7 0.17
2066-0A1 1 13 0.34
2066-0B1 1 20 0.48
2066-0C1 1 25 0.61
2066-0X2 2 28 0.71
2066-001 1 32 0.80
2066-0A2 2 44 1.20
2066-002 2 60 1.57
2066-003 3 84 2.32
2066-004 4 108 3.06

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zSeries 900 Models 1XX (zSeries 900 2064-1C1 = 1.00)
Processor #CP MSU CMS1
2064-101 1 41 0.98
2064-102 2 78 1.90
2064-103 3 112 2.81
2064-104 4 143 3.70
2064-105 5 173 4.59
2064-106 6 199 5.44
2064-107 7 225 6.22
2064-108 8 245 6.89
2064-109 9 j 265 7.39  a
2064-1C1 1 43 1.00
2064-1C2 2 83 1.96
2064-1C3 3 119 2.91
2064-1C4 4 153 3.86
2064-1C5 5 187 4.82
2064-1C6 6 217 5.75
2064-1C7 7 247 6.63
2064-1C8 8 276 7.42
2064-1C9 9 302 8.11  a
2064-110 10 327 8.78  a
2064-111 11 350 9.49  a
2064-112 12 372 10.22  a
2064-113 13 392 10.91  a
2064-114 14 410 11.57  a
2064-115 15 426 12.21  a
2064-116 16 441 12.85  a

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zSeries 900 Models 2XX (zSeries 900 2064-1C1 = 1.00)
Processor #CP MSU CMS1
2064-2C1 1 52 1.21
2064-2C2 2 100 2.38
2064-2C3 3 144 3.53
2064-2C4 4 184 4.67
2064-2C5 5 224 5.83
2064-2C6 6 260 6.96
2064-2C7 7 296 8.02
2064-2C8 8 330 8.98
2064-2C9 9 362 9.82  a
2064-210 10 392 10.63  a
2064-211 11 420 11.49  a
2064-212 12 445 12.36  a
2064-213 13 475 13.20  a
2064-214 14 497 14.00  a
2064-215 15 517 14.78  a
2064-216 16 535 15.54  a

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a Data is based on measurements of two VM images under LPAR. The LPAR configuration was two shared partitions, with each partition having ((N/2)+1) engines, where N is the number of CPs (if the number of CPs is even) or N is one less than the number of CPs (if the number of CPs is odd). For example, there were two shared partitions of 6 engines each for either a 2064-110 (10 way processor) or a 2064-111 (11 way processor).