Attention:

A four-digit feature code is used to specify a component that is configurable in the IBM configurators, the eBusiness Configurator (eConfig) and the IBM Web-based Hardware Configurator, used in US and Canada. Options that do not have feature codes cannot be integrated by IBM into a system using these IBM configurators. To purchase options separately, refer to the option part number provided in this document.

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number
Option
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Feature
code
Memory description
Memory DIMMs
49Y1379 49Y1397 8923 8GB (1x8GB, 2Rx4, 1.35V) PC3L-10600 CL9 ECC DDR3 1333MHz LP RDIMM
49Y1387 49Y1405 8940 2GB (1x2GB, 1Rx8, 1.35V) PC3L-10600 CL9 ECC DDR3 1333MHz LP RDIMM
49Y1388 49Y1406 8941 4GB (1x4GB, 1Rx4, 1.35V) PC3L-10600 CL9 ECC DDR3 1333MHz LP RDIMM
49Y1389 49Y1407 8942 4GB (1x4GB, 2Rx8, 1.35V) PC3L-10600 CL9 ECC DDR3 1333MHz LP RDIMM
49Y1386 49Y1404 8648 4GB (1x4GB, 2Rx8, 1.35V) PC3L-10600 CL9 ECC DDR3 1333MHz LP UDIMM
49Y1562 49Y1563 A1QT 16GB (1x16GB, 2Rx4, 1.35V) PC3L-10600 CL9 ECC DDR3 1333MHz LP RDIMM
49Y1558 49Y1559 A28Z 4GB (1x4GB, 1Rx4, 1.5V) PC3-12800 CL11 ECC DDR3 1600MHz LP RDIMM
90Y3108 90Y3109 A292 8GB (1x8GB, 2Rx4, 1.5V) PC3-12800 CL11 ECC DDR3 1600MHz LP RDIMM
90Y3104 - A291 32GB (1x32GB, 4Rx4, 1.35V) PC3L-10600 CL9 ECC DDR3 1333MHz LP LRDIMM
90Y3177 - A24L 4GB (1x4GB, 2Rx8, 1.5V) PC3-12800 CL11 ECC DDR3 1600MHz LP RDIMM
- 00D4968 - 16GB (1x16GB, 2Rx4, 1.5V) PC3-12800 CL11 ECC DDR3 1600MHz LP RDIMM

Table 1. Standard Memory Configuration
Model Std. DIMM Configuration
A2Y 2GB (1x2GB, 1Rx8, 1.35V) PC3L-10600 CL9 ECC DDR3 1333MHz LP RDIMM
B2Y, C2Y, D2Y, G2Y, H2Y, J2Y 4GB (1x4GB, 1Rx4, 1.35V) PC3L-10600 CL9 ECC DDR3 1333MHz LP RDIMM
EAY, EBY, ECY 8GB (1x8GB, 2Rx4, 1.35V) PC3L-10600 CL9 ECC DDR3 1333MHz LP RDIMM
A3Y, A5Y, A7Y, B3Y, B5Y, B7Y,F3Y 4GB (1x4GB, 2Rx8, 1.35V) PC3L-12800 CL11 ECC DDR3 1600MHz LP UDIMM
C3Y, G3Y 8GB (1x8GB, 2Rx8, 1.35V) PC3L-12800 CL11 ECC DDR3 1600MHz LP RDIMM

Table 2. DIMM Population Sequece (Mirrored Channel Mode)
CPU Slot
CPU 1 3,5 → 4,6
CPU 1 & CPU 2 3,5 → 9,11 → 4,6 → 10,12

Table 3. DIMM Population Sequence (Independent Mode)
CPU Slot
CPU 1 1 → 3 → 5 → 2 → 4 → 6
CPU1 & CPU2 1 → 7 → 3 → 9 → 5 → 11 → 2 → 8 → 4 → 10 → 6 → 12

Table 4. DIMM Population Sequence (Spare Channel Mode)
CPU Slot
CPU 1 1, 2 → 3, 4 → 5, 6
CPU1 & CPU 2 1,2 → 7,8 → 3,4 → 9,10 → 5,6 → 11,12

26 August 2014