|
IBM has a long history of leveraging technology to build high performance, reliable systems. Over the last several years, we have been increasingly applying this expertise to UNIX servers. The IBM eServer™ pSeries 680 continued this heritage with industry leading performance across a broad spectrum of industry standard benchmarks. The same microprocessor is used in the IBM eServer iSeries 840. That system is also at the head of the list in a number of industry standard benchmarks. The IBM RS/6000 SP system incorporating the POWER3-II microprocessor is currently used in the world's largest supercomputer at the Lawrence Livermore National Laboratory.
Several years ago, we set out to design a new microprocessor that would insure we would leverage IBM strengths across many different disciplines to deliver a server that would redefine what was meant by the term server. POWER4 is the result. It was developed by over 300 engineers in several IBM development laboratories.
With POWER4, the convergence of iSeries and pSeries microprocessors will reach a new level. POWER4 was designed from the outset to satisfy the needs of both of these systems. Additionally, projected technology improvements drove significant enhancements to system structure. The resulting design leverages technology advances in circuit densities and module packaging to achieve high levels of performance suitable for server types of applications. We have publicly talked about POWER4 for over 2 years prior to its formal announcement. We were confident we would achieve its objectives in terms of performance, schedule, and content. And we have.
In this paper, we first describe what drove the design. We then take a closer look at the components of the resultant systems from a microarchitecture perspective. We start by first discussing the POWER4 chip. One of our major strengths is system expertise and the ability to design multiple parts in a consistent and synergistic manner. In that light, POWER4 cannot be considered only a chip, but rather an architecture of how a set of chips are designed together to realize a system. As such, POWER4 can be considered a technology in its own right. In that light, we discuss how systems are built by interconnecting POWER4 chips to form up to 32-way symmetric multiprocessors (SMPs). The interconnect topology, referred to as a Distributed Switch, is new to the industry. Finally, no system discussion would be complete without some view of the reliability, availability and serviceability (RAS) features and philosophy incorporated into POWER4 systems. The RAS design is pervasive throughout the system and is as much a part of the design as is anything else.
| 
