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IBM's new POWER3 microprocessor integrates the high-bandwidth and floating point capabilities of its POWER2 architecture predecessor into a fully scaleable 64-bit PowerPC* symmetric multi-processor (SMP) implementation. Based on PowerPC Architecture*, this microprocessor contains the fundamental design features that are planned to be used in the CPUs for the next three generations of RISC System / 6000* targeted at the numeric intensive computing (NIC), high-end analysis, graphics, commercial workstation and server markets.
This paper provides an overview of how processor microarchitecture, silicon technology, packaging technology, and systems architecture can be leveraged to produce outstanding high-performance computational capabilities.
What follows is a description of the processor design point, the execution core, and key features - such as hardware prefetch - to reduce latency to memory.
*PowerPC, PowerPC Architecture, IBM RISC System/6000, RS/6000, POWER GTX3000P, POWER Architecture, POWER2 Architecture are trademarks of the IBM Corporation.
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