|
 
An early version of this paper has been submitted to the IBM Journal of Research and Development.
Introduction
IBM introduced the POWER-based RS/6000 workstation in February of 1990. This system was well received in the industry and helped IBM capture a sizable share of the workstation market. The POWER2 processor goals were to build on the strengths of the original POWER design and to overcome its shortcomings.
The POWER and POWER2 systems partition instruction processing across three units: the Instruction Cache Unit (ICU), the Fixed-Point Unit (FXU), and Floating-Point Unit (FPU). This paper describes the overall organization of the POWER2 ICU, as well as the improvements over the previous design. Figure 1 is a block diagram of the POWER2 ICU. The primary functions of the ICU are:
- Fetch all instructions
- Execute branch and logic on Condition Register instructions
- Dispatch instructions to the FXU and FPU
- Process interrupts
- Maintain the architected Condition, Count, and Link registers
- Maintain interrupt control registers
- Provide engineering support processor (ESP) functions.
To improve the performance over the existing POWER-based RS/6000 systems, the ICU designers focused on enhancing the branch performance and superscalar performance while minimizing the cache miss penalty. The POWER2 ICU design addressed these challenges by:
- Designing a new compare-branch scheme
- Adding a second branch processor to allow processing of two branches in a single cycle
- Increasing branch look-ahead capability
- Doubling the instruction fetch bandwidth both from cache and from memory
- Doubling the instruction buffers
- Enabling instruction cache accesses during cache miss processing
- Doubling the dispatch bandwidth to the other functional units.
Architected Registers
The ICU maintains the architected registers involved in processing branch instructions and interrupts. User-accessible registers include the Condition Register (CR), the Link Register (LR), and the Count Register (CTR). The other registers include the Machine State Register (MSR), the Save Restore Registers, and the Segment Registers.
Condition Register (CR)
The CR consists of eight 4-bit fields. The ICU tests these fields to determine the outcome of conditional branch instructions. Many events can modify the CR bits. Compare instructions can alter any field. Most register-to-register instructions include a record bit; setting the bit causes an update to a predefined CR field. Move to Condition Register instructions can alter any combination of the eight fields. Logic on Condition Register (LCR) instructions alter a single CR bit. Finally, the ICU can restore a previous CR value if an interrupt occurs.
The CR interlock logic provides a lock bit for each of the eight CR fields. Lock bits are set (reserving the corresponding fields) when the ICU dispatches CR setting instructions to the FXU or FPU; the lock bits are reset upon instruction completion. The ICU dispatches or holds instructions that read or update a CR field based on the setting of the lock bit associated with the source or target field.
Link Register (LR)
Subroutine calls use the LR extensively. A subroutine call usually translates into a branch instruction with its link bit set; the link bit specifies that the ICU must save the address of the next sequential instruction (the return address) in the LR. A special form of the branch instruction, which uses the contents of LR as the target address, supports returns from subroutine calls. Because the entire 32-bit value becomes the target address, this instruction also allows branching beyond the limitations of the normal branch displacement fields.
Count Register (CTR)
The 32-bit CTR serves multiple purposes. As its name implies, this register can hold the iteration count for a loop. A form of the branch conditional instruction decrements the count and tests the resulting value; the outcome affects whether the conditional branch is taken. Second, like the LR, the CTR also can supply the target address for long branches. Finally, across supervisor call boundaries, the save and restore process for the MSR involves the CTR.
Machine State Register (MSR)
Bits in the MSR enable or disable processor features such as external (and other) interrupt enables, privileged instruction access, FPU access, interrupt addressing, and instruction and data relocation.
Save Restore Registers
Save Restore Register 0 saves the return address on interrupts. Save Restore Register 1 saves the contents of the MSR and the interrupt status on interrupts; it restores the MSR during a return from interrupt instruction.
Segment Registers
The FXU maintains the sixteen segment registers which define the current effective-to-virtual address translation. The FXU broadcasts any segment register changes using the processor bus (PBUS). The ICU monitors the PBUS and maintains a shadow copy of these registers to improve the performance for instruction address translation.
Previous | Next
| 
