 
Introduction
The introduction of the RS/6000 Models 250, 58H, 590, and 990 marks a significant milestone in the successful POWER Architecture history. The Models 58H, 590, and 990 establish new workstation performance levels using the new POWER2 implementation of the POWER Architecture. The high-performance, low-cost Model 250 introduces the first PowerPC 601 implementation of the PowerPC Architecture.
The new models are upward compatible; existing POWER applications will run on all RS/6000 models with impressive performance. Furthermore, compiler enhancements can preserve binary compatibility across all platforms. For applications where optimal performance is desired and binary compatibility is not essential, the new release of the compilers allows the user to target specific implementations.
This article has four major components. The "Implementation Goals" section discusses the new systems in relation to the existing RS/6000 family. The "Architectural Relationship" section describes the differences in instruction sets for the chip implementations. The "Existing Application Binaries" section shows that users can obtain performance improvements on existing applications without recompilation. Finally, the "Considerations for Recompilation" section discusses the performance/compatibility tradeoffs when recompiling.
Implementation Goals
Before we describe compatibility issues, the relationship of the POWER2 and PowerPC 601 implementations in the RS/6000 family should be understood. The entire RS/6000 family originates from the POWER Architecture base as shown in Figure 1 . The POWER implementation can be found in models such as the 375, 580, and 980B. The RISC Single Chip (RSC) implementation of the POWER Architecture is found in the Models 220 and 230.
The POWER2-based systems, Models 58H, 590, and 990, improve both scientific and commercial performance on existing applications. POWER2's instruction extensions [1] can provide additional compute-intensive performance.
The PowerPC Architecture also leverages the POWER Architecture base and the existing RS/6000 applications. Motivations for the PowerPC Architecture changes included improved single-precision performance and multiprocessor support [2,3].
The dotted lines in Figure 1 indicate that the PowerPC 601 implementation used in the Model 250 "bridges" between the POWER and PowerPC Architectures. PowerPC 601's support of both architectures is described more in the following section. The future 603, 604, and 620 implementations of the PowerPC Architecture will support the PowerPC instruction set and will span a broader range of price/performance targets [3].
Architectural Relationship
Figure 2 provides a pictorial representation of the instructions implemented by the POWER, the POWER2, the PowerPC 601, and the other PowerPC implementations. The figure also indicates that the compiler's new -qarch option can select between the four sets of instructions.
The original POWER instruction set appears at the top of Figure 2. This set of POWER instructions will run on any RS/6000 platform, although some PowerPC platforms will emulate the instructions, resulting in lower performance.
The POWER2 implementation (second row) provides hardware Square Root, convert to integer, and quad-word load/store instructions. None of the additional instructions will run on the POWER and PowerPC implementations.
Consistent with the Reduced Instruction Set Computer (RISC) philosophy, the PowerPC Architecture (third row in Figure 2 ) removed several of the seldom-used POWER instructions. To maintain compatibility, the future PowerPC implementations (603, 604, and 620) will emulate the removed POWER instructions within the operating system. The additional PowerPC Architecture 32-bit instructions enable better single-precision floating-point performance and multiprocessing support. The PowerPC Architecture also defines a set of 64-bit instructions for future implementations. PowerPC's new instructions will not execute on the POWER and POWER2 implementations.
The PowerPC 601 processor provides a bridge between the POWER and PowerPC Architectures by supporting most of the PowerPC and POWER instructions (fourth row in Figure 2 ). The PowerPC 601 executes all compiler-generated user-level POWER instructions. The implementation also supports all but a few of the 32-bit PowerPC instructions. Existing binaries, which perform well on the PowerPC 601, may show a degradation on future PowerPC implementations which use emulation. However, the PowerPC 601 bridge allows time for software developers to recompile to a common set of instructions.
Existing Application Binaries
Binary compatibility allows existing applications to obtain performance and cost benefits of the new hardware without recompilation. Preserving binary compatibility is essential for allowing software application vendors flexibility as to when to recompile. This section describes the performance implications of running an existing application binary on the Models 250 and 590.
The relative performance of existing binaries is illustrated in Table 1 by the SPEC CFP92 suite of 14 floating-point benchmarks and the SPEC CINT92 suite of 6 integer benchmarks [4]. (For more information on the characteristics of the benchmark suites, see [5].) The gains on applications vary considerably depending on the amount of inherent parallelism and the data access characteristics. The baseline case for "existing application binaries" uses the -O option and compiles the SPEC benchmarks with the previous compilers, XL C (XLC) v1.2.1 and XL Fortran (XLF) v2.3. The -O option enables the level of optimization that the compiler designers believe represents a good tradeoff between compilation speed and run-time performance.
The Model 590 provides significant gains on both integer and floating-poi nt benchmarks. Table 1 shows that without recompilation, the SPEC CINT92 integer suite runs 47% faster on the Model 590 than the Model 580. The POWER2 implementation's dual fixed-point units exploit the inherent parallelism in the program. POWER2's larger data cache, faster clock rate, and improved branch characteristics also contribute to the performance improvement. The SPEC CFP92 floating-point suite runs 58% faster on the Model 590; the performance increase is due to POWER2's dual floating-point units, increased data cache, increased data and instruction cache line size, and larger translation look-aside buffers (TLBs).
The Model 250 performs well compared to the Model 580 on both integer and floating-point applications. Table 1 shows the SPEC CINT92 integer performance is 82% of a Model 580. Although the Model 250 runs at a slightly higher frequency, the Model 580's larger cache is the primary cause of the performance difference. On the SPEC CFP92 floating-point suite, the Model 250 achieves 53% of the Model 580 performance. The Model 580's larger cache and shorter floating-point pipeline are better suited to these floating-point codes, whereas the PowerPC 601 achieves a good cost/performance balance. Without recompiling, the PowerPC 601 can not exploit the single-precision instructions to achieve its full SPECfp92 potential.
Binary compatibility provides performance and cost benefits to existing applications without requiring recompilation.
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