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Get double the performance per core, plus improved processor utilization and availability for a more dynamic infrastructure.

Compare UNIX Servers. Learn the benefits of IBM Power Systems compared to competitive UNIX servers.

IBM POWER6™ processor-based Linux, i, and UNIX servers are designed to help you implement a dynamic infrastructure. The combination of leadership performance, energy efficiency, flexible virtualization features and RAS features are designed to reduce your cost, improve service to end users and reduce risk – especially for mission critical applications and highly virtualized, consolidated operating environments.

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Power availability

POWER™ processor-based systems have long been known for mainframe-inspired reliability, availability, and serviceability (RAS) features such as First Failure Data Capture. We extended that capability with the introduction of the POWER6 processor-based servers to include Processor Instruction Retry, Alternate Processor Recovery, Partition Availability priority, Live Application Mobility, and Live Partition Mobility. These features are designed to help enable you to eliminate systems related planned and unplanned outages. If you need to take a system down for reconfiguration, firmware updates or another reason, you will have the option of moving your applications to a different server without any impact to production operation. No reboots, no restarts, no service interruption — just continued outstanding service to your users.

Compare availability features

The table below compares the IBM POWER6 features to the features available on Integrity systems from HP and SPARC systems from Sun.

Feature¹	POWER6	SPARC	Integrity	Xeon
Application/Partition RAS
Partition Mobility	Yes	No	No	Yes
Application Mobility	Yes	No	No	No
Partition Availability priority	Yes	No	No	No
HW Isolated Partitions	No	Yes²	Yes²	No
System RAS
OS independent First Failure Data Capture	Yes	No	No	No
Redundant System Interconnect	No	Yes	No	No
Processor RAS
Processor Instruction Retry	Yes	Yes	No	No
Alternate Processor Recovery	Yes	No	No	No
Dynamic Processor Deallocation	Yes	Yes	Yes	No
Dynamic Processor Sparing	Yes	Yes¹	Yes¹	No
Memory RAS
Chipkill™	Yes	Yes	Yes	Yes
Redundant Memory	Yes⁴	Yes⁴	Yes⁴	Yes⁴
I/O RAS
Extended Error Handling	Yes	No	No	No

Application/Partition RAS features

Live Application Mobility is a feature of AIX® 6 that allows applications running in Workload Partitions (WPARs) to be moved from a WPAR to another WPAR without interrupting production operation. The target WPAR can be a different server. Live Partition Mobility is a feature of PowerVM Enterprise Edition that allows entire partitions including all of the applications running the operating environment of the partition to be moved from one server to another without interrupting production environment. Both of these features allow you to avoid planned outages when upgrades or maintenance is required.
Partition Availability priority is a feature of PowerVM that automatically shifts processor resource from low priority partitions to high priority partitions in case where the total processor resource has dropped below the minimum required for all partitions because of a dynamic processor deallocation. This shift is based on priorities set during the partition definition.
The POWER6 based servers use firmware to provide isolation between partitions. The firmware is designed to prevent a failure in an action or failure in a partition from impacting the operation of other partitions. The SPARC and Integrity both support hardware isolated partitions on some models. However these partitions are limited to a granularity of a system board in the case of the SPARC and a Cell in the case of the Integrity. In either case this is a minimum granularity of four processors.

Systems RAS features

First Failure Data Capture (FFDC) is designed to help fix problems faster and to avoid a second instance of the same problem. The feature uses thousands of bits in special registers to collect data about system status. These registers are not required for instruction execution and are frozen if a failure occurs.The information in the registers is used to help pinpoint the cause of the error.

Processor RAS features

If a processor failure occurs, the POWER6 based servers are designed to recover in many instances. Processor Instruction Retry is designed to retry the instruction in case of a soft failure. If the failure persists, Alternate Processor Recovery is designed to retry the instruction on a different processor. If the system either cannot recover or if a threshold of soft failures on a processor has been reached, then the system is designed to take that processor out of service using Dynamic Processor Deallocation. If there are spare processors in the system, either because they are not allocated to a partition or because they are inactive CoD processors, then the system is designed to automatically replace the processor it deallocated with a spare processor using Dynamic Processor Sparing.
Some versions of SPARC have an instruction retry, but none have Alternate Processor Recovery. Integrity has neither of those features. Both the SPARC and Integrity support dynamic sparing, but because of the granularity of the hardware isolation, the system board or the cell board with the spare processor have to be in the partition.

Memory RAS features

POWER6 servers use Redundant Bit Steering which uses spare memory chips to replace failing bits. These spare chips are part of the standard memory system design. The Integrity replaces failing pages with spare memory. Clients must purchase adequate spare memory for this feature to work. SPARC uses optional mirroring. Customer must purchase two times the memory they need for production to use this feature.

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¹ Analysis based on features described in: "IBM Power Platform Reliability, Availability, and Serviceability (RAS)", October 8, 2008, available at www.ibm.com, and “Meet the HP Integrity Superdome Server with the HP Super-Scalable Processor Chipset sx2000” and “Intel Itanium-based midrange servers from HP - The HP Integrity rx7640 and rx8640 Servers” available through www.hp.com (link resides outside of ibm.com). The Xeon features are described in specifications for Dell PowerEdge, HP ProLiant, and Sun x64 systems available at the respective Web sites: www.dell.com (link resides outside of ibm.com), www.hp.com (link resides outside of ibm.com), and www.sun.com (link resides outside of ibm.com). The Dell whitepaper “Dell™ PowerEdge™ Servers, 2009 – Memory” describing memory capability available at www.dell.com (link resides outside of ibm.com), and the Sun Whitepaper, “SUN FIRE™ X4170, X4270, AND X4275 SERVER ARCHITECTURE” available at www.sun.com (link resides outside of ibm.com) were also used as sources. The actual names of features vary between vendors. This comparison is based on the description of the features. Only features where there is a significant difference between vendors are included in the table. All vendors provide many more features such as redundant power, cooling, etcetera. All data is current as of April 21, 2009.

² Limited to HW partitions at the system board or cell board level. Sun Dynamic System Domains with use the Quad XSB are not hardware isolated.

³ SPARC and Integrity automatic recovery is limited. Alternative processor must be in the hardware partition or in HP's implementation must be in the partition or in a cell board that is not allocated to a partition. The Power system implementation allows any processor that is not currently allocated to be used.

⁴ Power uses Redundant Bit Steering which uses spare memory chips to replace failing bits. These spare chips are part of the standard memory system design. Integrity replaces failing pages with spare memory. Clients must purchase adequate spare memory for this feature to work. SPARC and Xeon systems uses optional mirroring. Customer must purchase two times the memory they need for production to use this feature.

^* All statements regarding IBM future directions and intent are subject to change or withdrawal without notice and represent goals and objectives only. Any reliance on these Statements of General Direction is at the relying party's sole risk and will not create liability or obligation for IBM.