System p education

The POWER5 processor is the first to introduce simultaneous multithreading (SMT) technology into the IBM Power Architecture™. There are two independent physical processors on a POWER5 chip. SMT provides two independent threads of instruction execution for each physical processor. Each thread appears to the operating system as a logical processor. Thus, turning on SMT mode makes one physical processor appear as two processors to the operating system and applications running in that partition.

In POWER5 processor-based systems, and in VLP, the user can turn SMT on or off on a per-logical-partition basis. SMT is best suited for highly threaded I/O-intensive commercial applications and is usually not beneficial for numerically intensive workloads. In VLP, if you request a one-CPU virtual server, and then turn on SMT, it will appear to the operating system and applications that you have a virtual server with two CPUs. Note that the two SMT processors share the entitled capacity of the one virtual CPU. AIX 5L V5.3 supports turning SMT on and off without rebooting. Other operating systems might require a reboot of the partition, either through the VLP reset OS or reset partition function or with a command-line equivalent, in order to switch SMT on or off.

SMT improves efficiency by using hardware resources that might not otherwise be fully exploited. The physical processor has two unique contexts with replication of many resources, such as registers and program counters. Instructions are fetched and dispatched on the basis of resource availability at the time of operation. This allows the interleaving of instruction streams, which enables concurrent instruction execution. For example, one thread can be executing an instruction comprising an integer operation, while the other might be executing a floating-point instruction. Each physical processor contains an L1 data cache and an L1 instruction cache, where both the caches are shared between the two logical processors. The four logical processors on the POWER5 processor-based system share the L2 cache. Hence, with this hierarchy, four threads share the same L2 cache, allowing concurrent processing of multiple cache fills to occur because of multiple threads.

The implementation of SMT on POWER5 processor-based systems is based on two threads of execution sharing the same cache hierarchy, and because the L1 instruction and data cache and the translation look-a-side buffers (TLBs) are smaller than the L2 and L3 caches, the cache miss rates will increase when SMT is enabled. This is particularly true when a workload relies on large binaries and multiple processes with a high degree of multiprogramming (and very large memory footprint). Consequently, the performance benefit achieved when enabling SMT varies, depending on the workload and the way the application is written. Internal benchmarks done by IBM show that many commercial workloads show an average of 25% to 40% performance improvement (these results only apply to applications running in dedicated servers without partitions).

Applications with multiple threads that intensively use a particular unit (or resource) of a processor usually do not benefit much from SMT. For example, scientific applications that extensively exercise floating-point calculations are known to benefit little from SMT. Workloads with very low cycle-per-instruction (CPI) ratios and low cache miss rates do not tend to improve their performances as much when SMT is enabled. By contrast, applications using many threads that have a high CPI ratio because of low cache hit rates, or those suffering from TLB misses, are likely to benefit from SMT. Workloads with low CPI ratios and low cache miss rates do not tend to improve their performances by enabling SMT.

SMT is available on POWER5 processor-based hardware running AIX 5L V5.3, Novell® Suse™ Linux SLES9, and Red Hat Linux Enterprise Level version 3.0. Unless specified otherwise in a particular VLP image, the default setting for SMT is off in VLP logical partitions, and, if desired, the user must explicitly enable it. If you enable SMT and save the image, SMT will still be on in the restored image. On AIX 5L V5.3, you can dynamically enable or disable SMT; however, on the Linux operating system it requires a system reboot. Enabling or disabling SMT is specific to a given partition, thereby allowing multiple concurrent partitions to run in different modes (single-threaded versus SMT, for example).

To control the SMT modes, AIX 5L V5.3 provides the smtctl command. It lets privileged users control application utilization of processors with SMT support. You can enable or disable SMT for all processors in a partition, immediately or on subsequent boots of the system. The syntax for the smtctl command is as follows:

smtctl [-m off | on [-w boot -ww now]]

• -m off: This option will set the SMT mode to disabled.
• -m on: This option will set the SMT mode to enabled.
• -w boot: This option makes the SMT mode change effective on the next and subsequent reboots.
• -w now: This option makes the SMT mode change immediately, but it will not persist across reboot. If neither the -w boot or the -w now options are specified, the mode change is immediate and will persist across subsequent boots.

On Linux operating systems, you can disable or enable SMT only by using a Linux boot console command and a system reboot. Instead of using a command such as the smtctl command, you need to append the following command line in the /etc/yaboot.conf file:

append="smt-enabled=off"

In VLP, you can then reboot the virtual server (LPAR) by using the reset partition or reset OS command found on the VLP Web site.