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IBM Extends Industry Leading Custom Chip Technology to Embedded Devices

New Low Power ASIC Offering Delivers as Much as 30X Improvement in Standby Power Management

ANAHEIM, CA - 13 Jun 2005: IBM today announced two new 65 nanometer (a nanometer is a billionth of a meter) application-specific integrated circuit (ASIC) product offerings, including the company's first ever comprehensive low power ASIC offering for the fast growing wireless, mobile and consumer electronics market. An ASIC is an integrated circuit customized for a particular use, rather than intended for general-purpose use. For example, a chip designed solely to run a cell phone is an ASIC.

Specifics of this dual offering were detailed today at the 2005 Design Automation Conference (DAC) in Los Angeles, CA:

"This dual offering will continue our undisputed logic ASIC technology leadership at the high end," said Tom Reeves, OEM vice president, Semiconductor Products for IBM Systems & Technology Group. "Now with the introduction of our low-power ASIC offering we will bring our proven record of technology leadership to the high growth consumer marketplace."

Innovations found in both Cu-65LP and Cu-65HP offerings include:

--Integrated noise, power, timing methodology that can help enable first pass success designs

--Voltage Island technique to control power

--Multiple threshold voltage library enables clients to balance performance and power requirements

The low power (Cu-65LP) design kit targeted availability is in the second quarter of 2005, followed by the high performance design kit planned for later in the year. Volume production for the Cu-65 low power and high performance offerings are planned in the first quarter and third quarter of 2007, respectively.

The offering includes standard-cell logic design libraries; multiple I/O families; embedded SRAM and DRAM; a diverse collection of cores, including industry leading high-speed SerDes and embedded microprocessors highlighting PowerPC Architecture, as well as a wide range of packaging solutions.

The IBM low power ASIC offering is built on top of industry standard ARM Artisan physical IP, specifically standard cells, SRAM memory compilers and general purpose I/Os. IBM's ASIC methodology is intended to enable fast design closure and help achieve first pass success designs. ARM, a provider of industry standard libraries, is co-developing these 65nm low power libraries with IBM.

Contact(s) information

Bruce McConnel
IBM Media Relations
(914) 766-4427
wmcconn@us.ibm.com

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