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  • Cross-section of 64-bit high-performance microprocessor chip

    Cross-section of 64-bit high-performance microprocessor chip


    Date added: 2005-12-05


    Cross-section of 64-bit high-performance microprocessor chip built in IBM's 90 nm Server-Class CMOS technology with Cu/low-k wiring. Above the transistors, the wiring levels include one W local interconnect, five "1x-scaled" Cu levels in full SiCOH low-k dielectric, three "2x-scaled" Cu/SiCOH levels, two "6x-scaled" Cu levels in FTEOS/SiO2 dielectric, and finally, one Al(Cu) terminal pad and wiring level. The minimum M1 Cu line widths and spaces are 0.12 um.

     

     

     



  • Cell microprocessor

    Cell microprocessor


    Date added: 2005-10-25


    IBM Analysis Engineer Tami Vogel holds a prototype of the new Cell microprocessor, a collaboration between engineering teams from IBM, Sony and Toshiba. Essentially a supercomputer on a chip, the Cell microprocessor is expected to transform consumer electronics and digital entertainment.

     

     

     


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