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Scientists Discover New Atomic Technique to Charge Memory Chips
Date added: 2013-03-22
Optical image of a typical ionic liquid (IL) gated device with a droplet of IL on top of the gate electrode and the oxide channel. The gold squares are pads used to make contact to the device via wire-bonding. On right is the magnified image of the device showing the channel (brownish yellow) and the gold electrical contacts (bright yellow). The contacts on the right and left of the channel are the source and drain contacts. The four other contact are used for 4-wire resistance & Hall measurements. (Credit: IBM)
Cross-section of 64-bit high-performance microprocessor chip
Date added: 2005-12-05
Cross-section of 64-bit high-performance microprocessor chip built in IBM's 90 nm Server-Class CMOS technology with Cu/low-k wiring. Above the transistors, the wiring levels include one W local interconnect, five "1x-scaled" Cu levels in full SiCOH low-k dielectric, three "2x-scaled" Cu/SiCOH levels, two "6x-scaled" Cu levels in FTEOS/SiO2 dielectric, and finally, one Al(Cu) terminal pad and wiring level. The minimum M1 Cu line widths and spaces are 0.12 um.
Date added: 2005-10-25
IBM Analysis Engineer Tami Vogel holds a prototype of the new Cell microprocessor, a collaboration between engineering teams from IBM, Sony and Toshiba. Essentially a supercomputer on a chip, the Cell microprocessor is expected to transform consumer electronics and digital entertainment.