Cross-section of 64-bit high-performance microprocessor chip
Date added: 05 Dec 2005
Cross-section of 64-bit high-performance microprocessor chip built in IBM's 90 nm Server-Class CMOS technology with Cu/low-k wiring. Above the transistors, the wiring levels include one W local interconnect, five "1x-scaled" Cu levels in full SiCOH low-k dielectric, three "2x-scaled" Cu/SiCOH levels, two "6x-scaled" Cu levels in FTEOS/SiO2 dielectric, and finally, one Al(Cu) terminal pad and wiring level. The minimum M1 Cu line widths and spaces are 0.12 um.