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Announced April 7, 1964 and withdrawn June 22, 1970.
Smallest of the System/360 configurations, the Model 30 could serve as a stand-alone system, a communications system or the satellite processor of a larger system.
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Decimal add (5 + 5 digits) |
13,300 |
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Fixed point add (1 word + 1 word) (32 bits) |
34,500 |
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Fixed point multiply (1 word x 1 word) |
3,300 |
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Fixed point divide (2 words div. by 1 word) |
1,800 |
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Floating point multiply (1 word x 1 word) |
3,200 |
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Speed |
Data width (bits) |
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Machine cycle time |
1 microsec. |
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Logic circuits |
30 nanosec. |
8 |
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Memory cycle time 8K, 16K, 32K, 64K |
2 microsec. |
8 |
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Registers 16 general purpose 4 floating point |
8 microsec. 16 microsecond |
32 64 |
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Control Read only storage Special 1401 compatible feature |
1 microsec. |
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Data rate per channel (Char. a Sec.) |
Control units per channel |
I/O units per channel |
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Channels: Selector (up to 2) |
250,000 |
8 |
256 |
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Multiplexor Multiplex mode Burst mode |
16,000 200,000 |
8 |
96 |
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