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Early System/370-Compatibles CPU characteristics*
Model Data Flow Width (bytes) Cycle Time (nanoseconds)
3031 4 115
3032 8 80
3033 8 57
3033-N 8 57
3033-S 8 57
3081 8 26
4331-1 4 300-1600 **
4331-2 4 200-1600 **
4341-1 8 150-300 **
4341-2 8 120-240 **

* Source: A. Pedegs, "System/360 And Beyond," IBM Journal Of Research And Development, Vol. 25, No. 5, September 1981, Table 1, p. 389.
** Variable, depending on the type of operation performed.

Early System/370-Compatibles control storage characteristics*
Model Size (K Words) Type Cycle Time (nanoseconds)
3031 8 RW 115
3032 4 RW 80
3033 3-7 RW 57
  1 RW 57
3033-N 3-7 RW 57
  1 RW 57
3033-S 3-7 RW 57
  1 RW 57
3081 2 (3) RW 52 (4)
4331-1 16-32 (2) RW 500 (1)
4331-2 32 (2) RW 500 (1)
  3 RO 100
4341-1 14-16 RW 150
4341-2 16-20 RW 120

K = 1024

RO = Read-only

RW = Read-write (writable)

(1) 100 nanoseconds when the word is available in the microinstruction buffer.

(2) Part of this capacity is physically in processor storage and thus has to be subtracted from the available processor-storage capacity.

(3) 1K of the control storage is pageable, using an area in processor storage assigned for this purpose.

(4) 26 nanoseconds when the word is available in the microinstruction buffer (i.e., is within the current set of 16 words).

* Source: A. Pedegs, "System/360 And Beyond," IBM Journal Of Research And Development, Vol. 25, No. 5, September 1981, Table 1, p. 389.

Early System/370-Compatibles processor storage characteristics*
Model Size (K bytes) Bus Width (bytes) Cycle Time (nanoseconds)
3031 2048-8192 8 x 4 345 (1)
3032 2048-8192 8 x 4 320
3033 4096-25576 8 x 8 285 (1)
3033-N 4096-16384 8 x 4 285
3033-S 4096-8192 8 x 4 285
3081 16384-32768 8 x 2 (4) 312 (2)
4331-1 512-1024 4 900 R
      1300 W
4331-2 1024-4096 4 2600 (3) R
      3100 (3) W
4341-1 2048-4096 8 2400 (3)
4341-2 2048-8192 16 1440 (3)

K = 1024
R = Access for reading.
W = Access for writing.

(1) The effective transfer rate to the CPU is limited to eight bytes per CPU cycle.
(2)  An amount equal to a cache line is read or written in one storage cycle. The effective transfer rate to the CPU is limited to eight bytes per CPU cycle.
(3) An entire cache line can be accessed and transferred between the cache and the storage unit in this time.
(4) Interleaving is on the basis of 2K bytes; no interleaving takes place within the access for a cache line of 128 bytes.

* Source: A. Pedegs, "System/360 And Beyond," IBM Journal Of Research And Development, Vol. 25, No. 5, September 1981, Table 1, p. 389.

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